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? semiconductor components industries, llc, 2002 june, 2002 rev. 2 1 publication order number ncp1560/d ncp1560 advance information full featured voltage mode pwm controller the ncp1560 pwm controller contains all of the features and flexibility needed to implement voltagemode control for modern high performance power converters. this device cost effectively reduces system part count with the inclusion of a high voltage startup regulator that operates over a wide input range of 33 v to 150 v. the ncp1560 provides two control outputs, out1 which controls the main pwm switch and out2 with adjustable overlap delay, which can control a synchronous rectifier. other distinctive features include: two mode over current protection, line under/over voltage lockout, fast line feedforward, softstart and a maximum duty cycle clamp. features ? internal high voltage startup regulator ? dual control outputs with adjustable overlap delay ? single resistor oscillator frequency setting ? fast line feedforward ? line under/over voltage lockout ? dual mode over current protection ? programmable maximum duty cycle control ? maximum duty cycle proportional to line voltage ? programmable softstart ? precision 5.0 v reference typical applications ? telecommunication power converters ? industrial power converters ? high voltage power modules ? +42 v automotive systems ? control driven synchronous rectifier power converters this document contains information on a new product. specifications and information herein are subject to change without notice. device package shipping ordering information ncp1560dr2 so16 2500 units/reel a = assembly location wl = wafer lot y = year ww = work week marking diagram 16 so16 d suffix case 751b ncp1560dr2 1 1 16 awlyww http://onsemi.com
ncp1560 http://onsemi.com 2 v in gnd uv/ov cs ff high voltage startup regulator fault detection oscillator delay logic modulator figure 1. simplified block diagram thermal shutdown 5.0 v reference v aux ss v ea t d r t output drivers out1 out2 uv dc max v ref cskip
ncp1560 http://onsemi.com 3 figure 2. ncp1560 block diagram + + 5.0 v reference v in gnd v ea thermal shutdown delay logic out1 + + + cs s r q reset dominant latch c ss 10 5 14 16 1 11 12 r d stop stop v in 17 ma disable c cskip 11 v/7 v clock disable_ss s r q reset dominant latch (250 ns) disable_ss c aux dis v aux v aux out2 v aux 15 13 v aux 10 pf ff ramp (adjustable) * laser trimmed during manufacturing to obtain 1.3 v with r t = 100 k v in r ff ff 4 + current mirror + r t 2 v 10 pf i 1 + 2 v 7 oscillator ramp 2 v + dis dis 8 + 2 v max dc comparator pwm comparator + softstart comparator 0.5 v + 0.6 v + ss 9 5 v one shot pulse 5 v + 6 cskip 3.6 v 1.49 v 2 uv/ov + 2 v + one shot pulse + + i 1 2 + 1.3 v* v ref t d 20 k 40 k v ref dc max 2 k 32 k 27 k 5.65 k 3.6 k + v dc(inv) r mdp r p c ff disable_v ref disable_v ref i ff disable 11 a + v + i v 62.5 k r t (600 ns) one shot pulse clock
ncp1560 http://onsemi.com 4 pin description pin name application information 1 v in this pin is connected to the bulk dc input voltage supply. a constant current source supplies current from this pin to the capacitor connected on the v aux pin. the charge current is typically 17 ma. input voltage range is 33 v to 150 v. 2 uv/ov input supply voltage is scaled down and sampled by means of a resistor divider. the supply voltage must be scaled down between 1.49 v and 3.60 v within the specified input voltage range. 3 nc not connected. 4 ff an external resistor between v in and this pin adjusts the amplitude of the ff ramp in proportion to v in . by varying the feedforward ramp amplitude in proportion to v in voltage, changes in loop bandwidth resulting from v in changes are eliminated. 5 cs over current sense input. if the cs voltage exceeds 0.47 v or 0.57 v, the converter enters cycle by cycle or cycle skip current limit mode, respectively. 6 cskip the capacitor connected to this pin sets the cs fault timer after a cycle skip current limit fault is detected. a softstart sequence will follow at the conclusion of the fault timer. 7 r t a single external resistor between this pin and gnd sets the fixed oscillator frequency. 8 dc max an external resistor between this pin and gnd sets the voltage on the max dc comparator inverting input. the duty cycle is limited by comparing the voltage on the max dc comparator inverting input to the feedforward ramp. 9 ss an internal 6.0 m a current source charges the external capacitor connected to this pin. the duty cycle is limited during startup by comparing the voltage on this pin to the oscillator ramp. 10 v ea the error signal from an external error amplifier is fed into this input and compared to the feedforward ramp. a series diode and resistor offset the voltage on this pin before it is applied to the pwm comparator inverting input. 11 v ref precision 5.0 v reference output. maximum output current is 10 ma. 12 t d an external resistor between v ref and this pin sets the leading and trailing edge time delay between out1 and out2 transitions. 13 out2 output of the pwm controller with leading and trailing edge time delay. out2 can be used to drive a synchronous rectifier. 14 gnd control circuit ground. 15 out1 main output of the pwm controller. 16 v aux positive input supply voltage. this pin is connected to an external capacitor for energy storage. an internal current supplies current from v in to this pin. once the v aux voltage reaches 11 v, the current source turns off. it turns on again once v aux falls to 7 v. power is then supplied to the ic via this pin, by means of an auxiliary winding.
ncp1560 http://onsemi.com 5 maximum ratings (note 1) rating symbol value unit input line voltage v in 0.3 to 150 v auxiliary supply voltage v aux 0.3 to 16 v out1 and out2 voltage v out 0.3 to v aux 0.8 v v out1 and out2 output current i out 10 ma 5.0 v reference voltage v ref 0.3 to 6.0 v 5.0 v reference output current i ref 10 ma dc max voltage v dcmax 0.3 to 2.0 v all other inputs/outputs voltage v io 0.3 to 5.5 v all other inputs/outputs current i io tbd ma operating junction temperature t j 40 to +150 c storage temperature range t stg 55 to +150 c power dissipation at t a = 25 c p d 0.88 w thermal resistance, junction to ambient r q ja 130 c/w 1. maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximumrated conditions is not implied. functional operation should be restricted to the recommended operating conditions. a. this device series contains esd protection and exceeds the following tests: pin 1: human body model 2000 v per milstd883, method 3015. pin 1: machine model method 150 v. pins 216: human body model 2000 v per milstd883, method 3015. pins 216: machine model method 200 v. pin 1 is the hv startup of the device and is rated to the max rating of the part, or 150 v. b. this device contains latchup protection and exceeds xx ma per jedec standard jesd78.
ncp1560 http://onsemi.com 6 electrical characteristics (v in = 48 v, v aux = 12 v, v ea = 2 v, r t = 100 k , c cskip = 6800 pf, r d = 60.4 k , r ff = 464 k , for typical values t j = 25 c, for min/max values, t j = 40 c to 125 c, unless otherwise noted) characteristic symbol min typ max unit startup control and v aux regulator v aux regulation startup threshold/v aux regulation peak (v aux increasing) minimum operating v aux valley voltage after turnon hysteresis v aux(on) v aux(off) v h tbd tbd 11 7.0 4.0 tbd tbd v startup circuit output current v aux = 0 v t j = 25 c t j = 40 c to 125 c v aux = v aux(on) 0.2 v t j = 25 c t j = 40 c to 125 c i start 11 tbd tbd tbd 17.6 tbd 16.6 tbd tbd tbd tbd tbd ma startup circuit offstate leakage current (v in = 150 v) t j = 25 c t j = 125 c i start(off) 18 10 50 tbd a auxilliary supply current after v aux turnon outputs disabled v ea = 0 v v uv/ov = 0 v outputs enabled i aux1 i aux2 i aux3 tbd 3.0 1.55 4.6 5.0 2.5 tbd ma line under/overvoltage detector undervoltage threshold (v in increasing) v uv 1.42 1.52 1.62 v undervoltage hysteresis v uv(h) 0.155 v overvoltage threshold (v in increasing) v ov 3.52 3.55 3.72 v overvoltage hysteresis v ov(h) 0.150 v undervoltage propagation delay to output t uv 250 ns overvoltage propagation delay to output t ov 160 ns line feedforward feedforward ramp amplitude v ff(pp) 2.7 v current limit and thermal shutdown cycle by cycle threshold voltage i lim1 0.44 0.47 0.50 v propagation delay to output (v ea = 2.0 v) v ccs = i lim1 to 2.0 v, measured when out1 reaches 10 v. t ilim 150 ns cycle skip threshold voltage i lim2 0.54 0.57 0.60 v cycle skip timer period t cskip 1.2 ms thermal shutdown threshold (junction temperature increasing) (note 2) t shdn 150 c thermal shutdown hysteresis (junction temperature decreasing) (note 2) t h 25 c 2. guaranteed by design only.
ncp1560 http://onsemi.com 7 electrical characteristics (v in = 48 v, v aux = 12 v, v ea = 2 v, r t = 100 k , c cskip = 6800 pf, r d = 60.4 k , r ff = 464 k , for typical values t j = 25 c, for min/max values, t j = 40 c to 125 c, unless otherwise noted) (continued) characteristic symbol min typ max unit oscillator frequency (r t = 100 k ) t j = 25 c t j = 40 c to 125 c f osc1 285 300 315 khz frequency (r t = 60.4 k ) t j = 25 c t j = 40 c to 125 c f osc2 500 khz maximum duty cycle comparator maximum duty cycle (v in = 36 v) r p = 0 , r mdp = open r p = open, r mdp = open r p = open, r mdp = 100 k d (max) 57 76 62 80 65 84 % softstart charge current (v ss = 1.0 v) i ss(c) 5.0 6.0 7.0 a discharge current (v ss = 5.0 v, v uv/ov = 3.75 v) i ss(d) 52.5 ma pwm comparator input bias current i ea 1.0 na lower input threshold v fb(l) 0.7 v delay to output (from x to x) t pwm 200 ns 5.0 v reference output voltage (i ref = 0 ma) t j = 25 c t j = 40 c to 150 c v ref 4.9 tbd 5.0 tbd 5.1 tbd v load regulation (i ref = 0 to 10 ma) v ref(load) 50 mv line regulation (v aux = 7 to 11 v) v ref(line) 50 mv control outputs overlap delay (t j = 25 c) rd = open leading trailing rd = 60 k leading trailing t d 220 170 85 70 ns output voltage low state (i sink = 10 ma) high state (i source = 10 ma) v ol v oh 0.25 11.0 v rise time (c l = 100 pf, 10% to 90%) t on 35 ns fall time (c l = 100 pf, 10% to 90%) t off 20 ns
ncp1560 http://onsemi.com 8 typical characteristics figure 3. auxiliary supply voltage thresholds versus junction temperature figure 4. startup circuit output current versus temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 25 50 5 6 7 8 9 10 11 12 125 100 75 50 25 0 25 50 10 11 12 13 14 15 16 20 figure 5. startup circuit output current versus auxiliary supply voltage figure 6. startup circuit output current versus line voltage v aux , auxiliary supply voltage (v) v in , line voltage (v) 12 10 8 6 4 2 0 15.0 15.5 16.0 16.5 17.0 17.5 18.0 19.0 150 125 100 75 50 25 0 0 4 8 12 16 20 figure 7. startup circuit offstate leakage current versus line voltage figure 8. auxiliary supply current versus junction temperature v in , line voltage (v) t j , junction temperature ( c) 150 125 100 75 50 25 0 0 4 8 12 16 20 24 32 125 100 75 50 25 0 25 50 0 0.5 1.0 1.5 2.0 2.5 3.5 4.0 v aux , auxiliary supply voltage (v) 150 150 17 18 19 i start , startup circuit output current (ma) 18.5 i start , startup circuit output current (ma) i start , startup circuit output current (ma) 28 i start(off) , startup circuit off state leakage current ( a) 150 3.0 i aux , auxiliary supply current (ma) startup threshold minimum operating threshold v aux = 0 v v aux = v aux(on) 0.2 v t j = 40 c t j = 25 c t j = 150 c t j = 40 c t j = 25 c t j = 125 c v ea = 0 v v uv/ov = 0 v v aux = 12 v v in = 48 v v in = 48 v v aux = 0 v v aux = 12 v
ncp1560 http://onsemi.com 9 typical characteristics figure 9. operating supply current versus junction temperature figure 10. line under/overvoltage thresholds versus junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 25 50 0 1 2 3 4 5 6 7 125 100 75 50 25 0 25 50 0 0.5 1.0 1.5 2.0 4.0 figure 11. line under/over voltage thresholds hysteresis versus junction temperature figure 12. maximum duty cycle versus feedforward current t j , junction temperature ( c) i ff , feedforward current ( a) 150 125 100 25 0 25 50 100 110 120 130 140 150 170 525 450 225 150 75 0 0 10 20 40 60 90 figure 13. feedforward internal resistance versus junction temperature figure 14. current limit thresholds versus junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 150 125 100 75 0 25 50 7.0 7.5 8.0 8.5 9.0 9.5 10.0 12.0 125 100 75 50 25 0 25 50 400 425 450 475 500 525 575 600 i aux3 , operating auxiliary supply current (ma) 150 150 2.5 3.0 3.5 v uv/ov , uv/ov voltage (v) 160 v uv/ov(h) , uv/ov threshold voltage hysteresis (mv) dc max , maximum duty cycle (%) 11.0 feedforward internal resistance (k ) 150 550 i lim , current limit thresholds (mv) 75 50 375 300 30 50 50 25 10.5 11.5 f osc = 420 khz uv threshold uv hysteresis t a = 40 c t a = 110 c ov threshold ov hysteresis cycle skip cycle by cycle v aux = 12 v f osc = 100 khz f osc = 87 khz 80 70 v in = 36 v r ff = 464 k v dcmax = 0 v
ncp1560 http://onsemi.com 10 typical characteristics figure 15. current limit propagation delay versus junction temperature figure 16. oscillator frequency versus junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 25 50 90 95 100 105 110 115 135 140 125 100 75 50 25 0 25 50 0 50 100 150 200 250 450 figure 17. oscillator frequency versus junction temperature figure 18. oscillator frequency versus timing resistor r t , timing resistor (k ) v in , line voltage (v) 400 300 250 200 150 100 50 0 100 200 300 400 600 76 66 56 46 36 20 30 40 60 70 100 figure 19. maximum duty cycle versus line voltage figure 20. maximum duty cycle versus junction temperature t j , junction temperature ( c) 150 125 100 75 0 25 50 50 60 70 80 90 t ilim , current limit propagation delay (ns) 150 150 300 350 400 f osc , oscillator frequency (khz) 500 f osc , oscillator frequency (khz) dc max , maxiimum duty cycle (%) 100 dc max , maximum duty cycle (%) 120 125 130 350 50 80 90 50 25 r t = 390 k r t = 100 k r t = 68 k r p = open, r mdp = 100 k to v ref r p = open, r mdp = open r p = 0 , r mdp = open r p = open, r mdp = open r p = 0 , r mdp = open r ff = 464 k t j = 25 c t j , junction temperature ( c) 125 100 75 50 25 0 25 50 285 290 295 300 305 310 150 315 f osc , oscillator frequency (khz) r t = 100 k v aux = 12 v measured from i lim1 to 10% of v oh t j = 25 c v in = 36 v r ff = 464 k
ncp1560 http://onsemi.com 11 typical characteristics figure 21. softstart charge/discharge currents versus junction temperature figure 22. maximum duty cycle versus error amplifier voltage v ea , error amplifier voltage (v) t j , junction temperature ( c) 1.6 1.4 1.2 1.0 0.8 0.6 0 10 20 30 40 50 60 70 125 100 75 50 25 0 25 50 4.97 4.98 4.99 5.00 5.02 figure 23. reference voltage versus junction temperature figure 24. outputs overlap delay versus junction temperature t j , junction temperature ( c) r d , delay resistor (k ) 75 50 25 0 25 50 0 50 100 150 200 250 350 1000 800 600 400 200 0 50 75 100 125 150 225 figure 25. outputs overlap delay versus delay resistor figure 26. outputs high state voltage versus junction temperature t j , junction temperature ( c) 150 125 100 25 0 25 50 10.0 10.2 10.4 10.6 10.8 11.0 11.6 12.0 dc max , maximum duty cycle (%) 1.8 150 5.01 v ref , reference voltage (v) 300 t d , outputs time delay (ns) t d , outputs time delay (ns) 11.8 v oh , outputs high state voltage (v) 150 125 100 175 200 50 75 11.2 11.4 i ref = 0 ma i ref = 10 ma r d = 1 m , leading r d = 1 m , trailing r d = 60 k , leading r d = 60 k , trailing leading trailing i source = 0 ma v in = 36 v v in = 48 v v in = 76 v i source = 10 ma v aux = 12 v t j , junction temperature ( c) 125 100 75 50 25 0 25 50 3.0 3.5 4.0 4.5 5.0 5.5 6.5 7.0 150 6.0 i ss(c) , softstart charge current ( a) i ss(d) , softstart discharge current (ma) 30 35 40 45 50 55 65 70 60 charge discharge t j = 25 c r ff = 464 k t j = 25 c r p = 0 , r mdp = open
ncp1560 http://onsemi.com 12 typical characteristics figure 27. outputs high state voltage versus output current figure 28. outputs rise time versus load capacitance c l , load capacitance (pf) 200 150 100 50 0 0 10 20 30 40 50 60 80 figure 29. outputs fall time versus load capacitance c l , load capacitance (pf) 200 150 100 50 0 0 5 10 15 20 25 35 70 t on , outputs rise time (ns) 30 t off , outputs fall time (ns) t j = 40 c t j = 25 c t j = 110 c t j = 40 c t j = 25 c t j = 110 c 175 125 75 25 175 125 75 25 i source , output source current (ma) 8 6 4 2 0 10.0 10.2 10.4 10.6 10.8 11.0 11.6 12.0 10 11.2 v oh , outputs high state voltage (v) 11.4 11.8 t j = 40 c t j = 25 c t j = 110 c v aux = 12 v detailed operating description the ncp1560 pwm controller contains all the features and flexibility needed for implementation of voltagemode control for modern high performance power converters. this device cost effectively reduces system part count with the inclusion of a high voltage startup regulator. the ncp1560 provides two control outputs, out1 which controls the main pwm switch and out2 with adjustable overlap delay, which can control a synchronous rectifier switch. other distinctive features include: two mode overcurrent protection, line under/over voltage lockout, fast line feedforward, softstart and a maximum duty cycle clamp. the functional block diagram is shown in figure 2. the ncp1560 is designed for voltagemode control converters. the features included in the ncp1560 enable all of the advantages of currentmode control, fast line feedforward, and cycle by cycle current limit. it eliminates the disadvantages of low power jitter, slope compensation and noise susceptibility. finally the dual outputs of the ncp1560 allow for optimum control of a synchronous rectifier switch. high voltage startup regulator the ncp1560 contains an internal high voltage startup regulator that eliminates the need for external startup components. in addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. the startup regulator consists of a constant current source that supplies current from the input line voltage (v in ) to the capacitor on the v aux pin (c aux ). the startup current is typically 17 ma. once v aux reaches 11 v, the outputs are
ncp1560 http://onsemi.com 13 allowed to turn on, as long as no faults are present. once v aux reaches 7 v again, the outputs are immediately disabled with no overlap delay and the startup regulator turns on. this a711o mode of operation is known as dynamic self supply (dss). as the dss sources current to the v aux pin, a diode should be placed between c aux and the auxiliary winding as shown in figure 30. this will allow the ncp1560 to charge c aux while preventing the startup regulator from biasing the auxiliary winding circuit. figure 30. recommended v aux configuration 17 ma disable c aux i aux v aux i aux to auxiliary winding v in the v aux pin can be biased externally above 7 v once the main output starts switching to prevent the startup regulator from turning on. it is recommended to bias the v aux pin using an auxiliary winding. an independent voltage supply can also be used. however, if v aux is biased before the outputs start switching or when a fault is present, the one shot pulse generator (figure 2) won't be enabled and the outputs will remain off. power to the controller while operating in the selfbias mode is provided by c aux . therefore, c aux must be sized such that a v aux voltage greater than 7 v is maintained while the outputs are switching and the converter reaches regulation. also, the v aux discharge time must be greater that the softstart charge period to assure the converter turns on. the startup circuit is rated at a maximum voltage of 150 v. if the device operates in the dss mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. line under/over voltage shutdown the ncp1560 incorporates a line under/over voltage shutdown (uv/ov) circuit. the under voltage (uv) threshold is 1.49 v and the over voltage threshold (ov) is 3.60 v, for a ratio of 1:2.4. the uv/ov circuit can be biased using an external resistor divider connected to the input voltage line. the resistor divider must be sized to enable the controller once v in is within the required operating range. if the uv or ov threshold is reached, the softstart capacitor is discharged, and the outputs are immediately disabled with no overlap delay as shown in figure 31. also, if an uv condition is detected, the 5.0 v reference supply is disabled. figure 31. uv/ov fault timing diagram uv or ov fault out2 out1 0 v 0 v 0 v 0 v v ov v uv uv/ov voltage v aux(off) v aux(on) v aux propagation delay to outputs (t uv or t ov )
ncp1560 http://onsemi.com 14 once the uv or ov condition is removed, the controller initiates a softstart cycle and allows the outputs to switch once v aux reaches 11 v. figure 32 shows the relationship between the uv/ov voltage, the outputs and the softstart voltage. figure 32. softstart timing diagram (using auxiliary winding) v aux(off) v aux(on) v aux 0 v 0 v 2 v 0 v 0 v 0 v out2 out1 softstart voltage uv/ov voltage softstart the uv/ov pin can also be used to implement a remote enable/disable function. biasing the uv/ov pin below its uv threshold disables the converter. feedforward ramp generator the ncp1560 incorporates line feedforward (ff) to compensate for changes in line voltage. a ff ramp proportional to v in is generated and compared to v ea . if the line voltage changes, the ff ramp slope changes accordingly. the duty cycle will be adjusted immediately instead of waiting for the line voltage change to propagate around the system and be reflected back on v ea . a resistor between v in and the ff pin (r ff ) sets the feedforward current (i ff ). the ff ramp is generated by charging an internal 10 pf capacitor (c ff ) with a constant current proportional to i ff . the ff ramp is finished (capacitor is discharged) once the oscillator ramp reaches 2.0 v. please refer to figure 2 for a detailed description of the feedforward ramp generator. i ff is usually a few hundred microamps, depending on the operating frequency and the required duty cycle. if the operating frequency and maximum duty cycle are known, i ff is calculated using the equation below: i ff c ff v dc(inv) 62.5 k 3.6 k t on(max) where v dc(inv) is the voltage on the inverting input of the max dc comparator and t on(max) is the maximum on time. figure 12 shows the relationship between i ff and dc max at 36 v. for example, if a system is designed to operate at 300 khz, with a 60% maximum duty cycle, dc max pin is grounded and a minimum line voltage of 36 v, i ff is calculated as follows: t 1 f 1 300 khz 3.33 s t on(max) dc max t 0.6 3.33 s 2.0 s i ff c v dc(inv) 62.5 k 3.6 k t on(max) 10 pf 0.888 v 62.5 k 3.6 k 2.0 s 77.2 a if the minimum line voltage is 36 v, the required feedforward resistor is calculated using the equation below: r ff v in i ff 9.25 k 36 v 77.2 a 9.25 k 464 k from the above calculations it can be observed that i ff is controlled predominantly by the value of r ff , as the feedforward internal resistance is only 9.25 k w . if a tight maximum duty cycle control over temperature is required, r ff should have a low thermal coefficient.
ncp1560 http://onsemi.com 15 current limit the ncp1560 has two over current protection modes, cycle by cycle and cycle skip. it allows the ncp1560 to handle momentary and hard shorts differently for the best tradeoff in p erformance and safety. the outputs are disabled typically 120 ns after a current limit fault is detected. the cycle by cycle mode terminates the conduction cycle (reducing the duty cycle) if the voltage on the cs pin exceeds 0.47 v. the cycle skip mode is enabled if the voltage on the cs pin reaches 0.55 v. once a cycle skip fault is detected, the outputs are turned off, the softstart and cycle skip capacitors are discharged, and the cycle skip period (t cskip ) commences. the cycle skip period is set by an external capacitor (c cskip ). once a cycle skip fault is detected, the cycle skip capacitor is discharged followed by a charge cycle. the charge current is 11 m a. the cycle skip period ends when the voltage on the cycle skip capacitor reaches 2.0 v. the cycle skip period is calculated as follows: c cskip t cskip 2v 11 a using the above equation, a cycle skip period of 12.3 m s requires a cycle skip capacitor of 68 pf. the differences between the cycle by cycle and cycle skip modes can be observed in figure 33. figure 33. over current faults timing diagram cycle skip voltage 0 v 0 v 0 v 0 v 0 v out2 out1 i lim2 i lim1 v aux(on) v aux(off) v aux cs voltage normal operation i lim2 reset i lim1 softstart normal operation t cskip once the cycle skip period is complete and v aux reaches 11 v, a softstart sequence commences. the minimum possible off time is set by c cskip . however, the actual off time is generally greater than the cycle skip period because it is the cycle skip period added to the time it takes v aux to reach 11 v. oscillator the ncp1560 oscillator frequency is set by a single external resistor connected between the r t pin and gnd. the oscillator is designed to operate up to 500 khz. the voltage on the r t pin is laser trim adjusted during manufacturing to 1.3 v for an r t of 100 k w . a current set by r t generates an oscillator ramp by charging an internal 10 pf capacitor as shown in figure 2. the period ends (capacitor is discharged) once the oscillator ramp reaches 2.0 v. if r t increases, the current and the oscillator ramp slope decrease, thus reducing the frequency. if r t decreases, the opposite effect is obtained. figure 17 shows the oscillator frequency vs r t .
ncp1560 http://onsemi.com 16 maximum duty cycle a dedicated internal comparator limits the maximum on time of out1 by comparing the ff ramp to the voltage on the inverting terminal of the max dc comparator. if the ff ramp voltage exceeds v dc(inv) , the output of the max dc comparator goes high. this w ill reset the output latch, thus turning off the outputs and limiting the duty cycle. by definition, duty cycle is defined as: dc t on t t on f therefore, the maximum on time can be set to yield the desired dc if the operating frequency is known. the maximum on time is set by adjusting the ff ramp to reach v dc(inv) in a time equal to t on(max) as shown in figure 34. the maximum on time should be set for the minimum line voltage. as line voltage increases, the slope of the ff ramp increases. this reduces the duty cycle below dc max , which is a desirable feature as the duty cycle is inversely proportional to the line voltage. figure 34. maximum on time limit waveforms oscillator ramp 0 v 0 v ff ramp t t on(max) v dc(inv) 2 v an internal resistor divider from a 2.0 v reference is used to set v dc(inv) . if the dc max pin is grounded, v dc(inv) is 0.88 v. if the pin is floating, v dc(inv) is 1.19 v. this is equivalent to 60% or 80% of a 1.5 v ff ramp. v dc(inv) can be adjusted to other values by using an external resistor network on the dc max pin. for example, if the minimum line voltage is 36 v, r ff is 464 k w , operating frequency is 300 khz with a maximum duty cycle of 70%, v dc(inv) is calculated as follows: v dc(inv) i ff 3.6 k t on(max) c ff 62.5 k v dc(inv) 77.2 a 3.6 k 2.33 s 10 pf 62.5 k 1.03 v this can be implemented by connecting a 16.9 k w resistor from the dc max pin to gnd. the maximum duty cycle limit can be disabled connecting a 100 k w resistor between the dc max and v ref pins. 5.0 v reference the ncp1560 includes a precision 5.0 v reference output. the reference output is biased directly from v aux and it can supply up to 10 ma. line and load regulation are 50 mv within the specified operating range. it is recommended to bypass the reference output with a 0.1 m f ceramic capacitor. the reference output is only disabled when an uv fault is detected. pwm comparator the output of an external error amplifier is compared to the ff ramp by means of the pwm comparator. the external error amplifier drives the v ea input. there is a 0.65 v offset between the v ea input and the pwm comparator inverting input. the offset is provided by a series diode and resistor. if the voltage on the v ea input is below 0.65 v, the pwm comparator output is high and the outputs turn off. the pwm comparator controls the duty cycle by turning off the outputs once the ff ramp voltage exceeds the offset v ea voltage. softstart the softstart (ss) feature allows the converter to gradually reach steady state operation, thus reducing startup stresses and surges on the system. the duty cycle is limited during a softstart sequence by comparing the oscillator ramp to the ss voltage (v ss ) by means of the softstart comparator. a 6.0 m a current source starts to charge the capacitor connected to the ss pin once no faults are present and v aux reaches 11 v. the softstart comparator controls the duty cycle as long as the ss voltage is below 2.0 v. once v ss is above 2.0 v, it exceeds the oscillator ramp voltage and the duty cycle is not limited any more by the softstart comparator. figure 35 shows the relationship between the outputs duty cycle and the softstart voltage. figure 35. softstart timing diagram out1 out2 v ss oscillator ramp if the softstart period is too long, v aux will discharge to 7 v, turning off the outputs before the converter output is completely in regulation. if the converter output is not completely discharged when the outputs are reenabled, the converter will eventually reach regulation exhibiting a nonmonotonic startup behavior. but, if the converter output is completely discharged when the outputs are reenabled, the cycle will repeat and the converter will not start.
ncp1560 http://onsemi.com 17 in the event of a uv, ov, thermal shutdown, or cycle skip fault, the softstart capacitor is discharged. once the fault is removed, a softstart cycle commences. the softstart steady state voltage is approximately 4.1 v. control outputs the ncp1560 has two inphase control outputs, out1 and out2, with adjustable overlap delay (t d ). out2 precedes out1 during a low to high transition and out1 precedes out2 at any high to low transition. figure 36 shows the relationship between out1 and out2. figure 36. control outputs timing diagram t d (trailing) t d (leading) out1 out2 generally, out1 controls the main switching element. out2, once inverted, can drive the free wheeling synchronous rectifier switching element. the overlap delay prevents simultaneous conduction. once v aux reaches 11 v, the internal startup circuit is disabled and the one shot pulse generator is enabled. if no faults are present, the outputs turn on. otherwise, the outputs remain off until the fault is removed and v aux reaches 11 v again. the control outputs are biased from v aux . the outputs can supply up to 10 ma each and their high state voltage is usually 0.8 v below v aux . therefore, the control outputs load should be considered when designing the auxiliary winding supply. if the control outputs need to drive a large capacitive load, a driver should be used between the ncp1560 and the load. the mc33152 is a good selection for an integrated driver. figures 28 and 29 shows the relationship between the output rise and fall times vs capacitive load. time delay the overlap delay between the outputs is controlled using a single resistor (r d ) between the t d and v ref pins. a minimum time delay of 80 ns is obtained when r d is 60 k w . if r d is not present, the delay is 210 ns. the output duty cycle can be adjusted from 0% to 100% selecting appropriate values of r ff and v dc(inv) . it should be note that out2 will reach 100% duty cycle before out1 because of the overlap delay. therefore, if out2 is used to control a synchronous rectifier, the maximum duty cycle needs to be less than 100% depending on the selected t d . the allowable time delay depends on the maximum duty cycle and frequency of operation. the maximum time delay is calculated using the equation below. t d(max) (1 dc) 2f for example, if the converter operates at a frequency of 300 khz with a maximum duty cycle of 80%, the maximum allowed time delay is 333 ns. however, this is a theoretical limit and variations over the complete operating range should be considered. thermal protection internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. when activated, typically at 150 c, the controller is forced into a low power reset state, discharging the softstart capacitor and disabling the output drivers and the bias regulator. once the junction temperature falls below 125 c, the ncp1560 enters a softstart mode and it is allowed to resume normal operation. this feature is provided to prevent catastrophic failures from accidental device overheating.
ncp1560 http://onsemi.com 18 - + - + n/c uv/ov cskip gnd 4 5 15 13 10 8 9 7 c28 1000 p c8 0.1 c7 10 5 v ref r5 c5 0.1 c6 0.01 r4 47.5 k on/off e3 r7 110 k c9 2200 p r8 0 (short) r13 121 k r14 14.3 k 1 3 2 16 11 12 6 14 r9 10 k rt ss out2 out1 cs v in v aux v ref t d c1 2.0 c2 2.0 c3 2.0 c4 2.0 c27 0.1 l1 10 h e1 v in e2 r1 1 m r2 100 r3 523 k c11 1000 p r10 100 r11 6.8 d8 1n914 v aux 1n914 d2 c10 0.1 d6 murs120t3 r32 15 d1 1n914 r12 10 k xt1 1:100 c22 1000 p r27 6.2 r25 10 k mtb1306 x4 r23 0 (short) x3 mtb1306 1000 p c21 r26 6.2 r24 10 k c20 330 c19 330 c18 47 c17 47 c16 47 c15 47 l2 2 h r28 0 (short) d7 1n914 x5 2n2907 mtb20n20e x1 r16 10 k c12 0.1 0 (short) r15 c14 0.1 1n914 d3 2 3 r18 5.1 k 5 v ref 1 4 c23 0.1 1n914 d5 tx3 ff v ea 8 7 6 5 1 2 3 4 n/c in_a gnd in_b n/c out_a out_b v cc u2 mc33152 u5 cs8271 gnd gnd adj v in gnd gnd sd v out 8 7 6 5 1 2 3 4 3.3 v out e5 e4 10 r31 100 p c29 sec_pwr r30 10 k r19 10 k u6b lm358 1000 p c30 u3 tlv431 0.1 c31 7 d9 1n914 r29 5.1 k 110 k 150 k r22 3 4 5 c25 0.1 c24 470 p r20 2 k r6 1 k r21 249 k 65 1 23 48 u4 sfh6156a4 figure 37. 100 w reference design u6a lm358 sec_pwr 1t 6,7 8,9 5t 3t 2t 45 10 2 111 u1 ncp1560 + + v aux v aux dc max
ncp1560 http://onsemi.com 19 reference design bill of materials quantity reference part/description value vendor notes 4 c1 c4 ckg45dx7r2a225m 7 d1 d3, d5, d7d9 mmbd914lt1 high speed diode 1 d6 murs120t3 ultrafast rectifier, 200 v 8 c8,c10,c12,c14, c23,c25,c27,c31 c1206c104k5rac 0.1 f, 50 v 4 c15 c18 c4532x5r0j476m 4.7 f, 6.3 v 2 c19 c20 t495x337k006as 330 f, 6.3 v 5 c11, c21, c22, c28, c30 c0805c102k1rac 1000 pf, 100 v 1 c5 c3216x7r2a104k 0.1 f, 100 v tdk 1 c6 c0805c103k5rac 0.01 f, 50 v kemet 1 c7 c5750x7r1e106m 10 f, 25 v tdk 1 c9 vj1206y222kxxa 2200 pf, 25 v vishay 1 c24 c0805c471j1gac 470 pf, 100 v kemet 1 c29 c0805c101j1gac 100 pf, 100 v kemet 1 r1 crcw1206105j 1 m 2 r2, r10 crcw1206101j 100 1 r3 rk73h2b5233f 523 k 1 r4 rk73h2b4752f 47.5 k 1 r5 crcw12061003f 100 k 1 r6 crcw1206102j 1 k 1 r7 crcw12061103f 110 k 4 r8, r15, r23, r28 0 short 1 r9 crcw1206103j 10 k 1 r11 crcw12066r81f 6.81 5 r12, r16, r19, r24, r25 crcw1206103j 10 k 1 r13 crcw12061213f 121 k 1 r14 crcw12061432f 14.3 k 2 r18, r29 crcw1206512j 5.1 k 1 r20 crcw1206202j 2.0 k 1 r21 crcw12062493f 249 k 1 r31 crcw1206100j 10 1 r32 1w015 15 resistornte 1 watt 1 tx1 cs105 vanguard electronics current transformer 1 tx2 9452 (custom) payton power transformer 1 tx3 gd103 vanguard electronics isolation transformer 1 u1 ncp1560 on semiconductor pwm controller 1 u2 mc33152 on semiconductor dual mosfet driver 1 u3 tlv431asnt1 on semiconductor voltage regulator 1 u4 sfh61564 infineon optocoupler 1 u5 cs8271 on semiconductor voltage regulator 1 u6 lm358d on semiconductor dual opamp 1 x1 mtb20n20e on semiconductor power mosfet, 200 v 2 x3, x4 mtb1306 on semiconductor power mosfet, 30 v 1 x5 mmbt2907awt1 on semiconductor pnp transistor 1 l1 do3316103 10 h coilcraft input choke 1 l2 9453 (custom) 2 h payton output choke
ncp1560 http://onsemi.com 20 package dimensions so16 d suffix case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncp1560/d the product described herein (ncp1560) may be covered by one or more u.s. patents. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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